1. Field of the Invention
The present invention relates in general to integrated circuit crosspoint switches and in particular to a crosspoint switch array composed of interconnected crosspoint switch arrays.
2. Description of Related Art
An Nxc3x97M crosspoint switch, such as disclosed for example in U.S. Pat. No. 5,790,048 issued Aug. 4, 1998 to Hsieh et al, employs an array of pass transistors to selectively route input signals arriving at any of N input ports to any of M output ports. FIG. 1 illustrates a simplified example 4xc3x974 crosspoint switch 10 as might be implemented within a single integrated circuit. Crosspoint switch 10 includes a set of four input signal drivers D0-D3 acting as input ports, a set of four receivers R0-R3 acting as output ports, a switch cell array 12 for selectively providing signal paths between drivers D0-D3 and receivers R0-R3, and array controller 14. Array 12 includes four rows and four columns of switch cells 16. Each of four conductive input lines H0-H3 lines deliver the output of a separate one of drivers D0-D3 to a separate row of switch cells 16. Each of four conductive output lines V0-V3 lines link a separate column of switch cells 16 to an input of a separate one of receivers R0-R3. Each switch cell 16 can selectively provide a signal path between one of input lines H0-H3 and one of output lines V0-V3. Controller 14 writes single bit control data into a memory cell within each switch cell 16, and the state of the bit controls whether or not the cell is to provide the signal path. Commands arriving on a control bus 22 from an external source such as a host computer tell controller 14 how to set the states of the control bits stored in the various switch cells 16.
For example, when driver D0 receives input signal IN(0) arriving at one of switch input terminals 18, it buffers the signal onto its corresponding input line H0. Each one of the four switch cells 16 that are linked to driver input line H0 and that are currently configured by their stored control data bit to provide a signal path, then forwards the signal to one of receivers R0-R3 via its corresponding output line V0-V3. Each receiver R0-R3 that receives the signal then buffers the signal onto one of four switch output terminals 20 as one of output signals OUT(0)-OUT(3).
FIG. 2 illustrates in more detail the upper left hand switch cell of the prior art crosspoint switch 10 of FIG. 1, including driver D0, input line H0, output line V0 and switch cell 16 linking input line H0 to output line V0 and receiver R0. Switch cell 16 includes a pass transistor Q having its source terminal S connected to input line H0 and its drain terminal D connected to output line V0. Switch cell 16 also includes a memory cell 25 for storing control data. A controller (not shown) uses control line 24 to write a bit into memory cell 25 of cell 16. Transistor Q passes signals from input line H0 to output line V0 when the bit in memory cell 25 turns transistor Q on and inhibits a signal on line H0 from passing to output line V0 when the bit turns transistor Q off.
Although for simplicity array 12 is illustrated as a 4xc3x974 switch cell array, switch cell arrays of similar design can be expanded to provide flexible routing paths between much larger numbers of input and output ports. Regardless of the dimensions of crosspoint switch 10, we would like the crosspoint switch to route signals with as little delay as possible. However crosspoint switch 10 can exhibit significant signal path delay which can increase as we increase the Nxc3x97M dimensions of array 12.
Referring again to FIG. 2, assume that pass transistor Q of the switch cell 16 linking input line H0 to output line V0 is on and that the pass transistors of all other switch cells in the array are off. When input signal IN(0) to driver D0 changes state, output signal OUT(0) produced by receiver R0 will also change state with a time delay that is the sum of the inherent delays of driver D0 and receiver R0 and the signal path delay through switch cell array 12. The signal path delay arises in large part because the output signal produced by driver D0 on line H0 must charge or discharge all of the shunt capacitance of the input line H0 and output line V0 before it can force receiver R0 to drive OUT(0) to another state. That shunt capacitance includes not only the inherent capacitances of those lines and the input capacitance of receiver R0, it also includes the capacitance associated with all transistors connected to both input line H0 and output line V0.
FIG. 3 is an impedance model of the pass transistor Q of the switch cell 16 illustrated in FIG. 2. Input line H0 and output line V0 of the array are connected to the source S and drain D terminals of transistor Q respectively. The gate of transistor Q is represented by a series channel resistance RC. When transistor Q is on the series resistance is small and the switch cell provides a low impedance signal path between input line H0 and output line V0. When pass transistor Q turns off, series channel resistance RC becomes large, thereby essentially breaking the signal path between input and output lines H0 and V0. Regardless of the switching state of transistor Q, the driver D0 of FIG. 1 that buffers input signal IN(0) onto input line H0 must charge the shunt capacitance CS at the transistors source terminal S. When transistor Q is on, driver D0 must also charge the shunt capacitance CD at the drain terminal D of transistor Q.
FIG. 4 is a simple model of the capacitive loading the 4xc3x974 array shown in FIG. 1 places on driver D0 when the upper left hand switch cell 16 is closed (its transistor Q being turned on to provide a signal path between the H0 and V0 lines) while all the other cells connected to lines H0 and V0 are open. When IN(0) is high the output stage of driver D0 connects line H0 through a load resistor RL1 to a positive voltage source VCC. When IN(0) is low, driver D0 grounds line H0 through a load resistor RL2.
To cause the output receiver R0 to drive the OUT(0) signal high or low, input driver D0 must charge or discharge the source terminal capacitances CS of all four switch cells 16 of FIG. 1 tied to input line H0, the drain terminal capacitances CD of all four switch cells 16 tied to output line V0, and the input capacitance of output receiver R0. Since charging or discharging all of that capacitance takes time, their is a delay between a change in state of the IN(0) signal and there is a corresponding change in state of the OUT(0) signal.
When we increase the size of the array, for example from 4xc3x974 to 8xc3x978, input and output lines H0 and V0 will each be connected to eight cells, rather than four. Thus driver D0 will have to charge or discharge eight, rather than four, source capacitances and eight, rather than four, drain capacitances. Thus the signal path delay through a crosspoint switch increases with the size of the switch.
A driver charges a capacitor at a rate in inverse relation to the product of its capacitance and the series resistance between the driver""s voltage source and the capacitor. Thus one way to reduce the signal path delay through array 12 is to increase the size of drivers D0-D3 (i.e., reduce the size of their load resistors RL1 and RL2 so that they can conduct more current when charging and discharging capacitance). This reduces the time the drivers need to charge or discharge the capacitance of array 12, thereby reducing signal path delay. However since there are practical limits to how much current a driver can supply, we need to provide other ways to further reduce signal path delay.
We could also reduce signal path delay by reducing the capacitance of pass transistors Q by making them smaller. However, smaller pass transistors have higher channel resistance. Since charging rates is proportional to the product of capacitance and resistance, increasing channel resistance tends to offset the effects of reducing channel capacitance. Therefore, while we can attain some delay reduction by optimizing the tradeoff between the capacitance and resistance of pass transistors Q, there are limits to this approach as well.
Therefore it would beneficial to provide yet another way to attain further reductions in signal path delay through array 12. What is needed is an architecture for a large crosspoint switch that helps reduce signal path delay.
An Nxc3x97M crosspoint switch in accordance with the invention routes input signals from any of N input terminals to one or more of M output terminals. The crosspoint switch includes N drivers, M receivers, and a crosspoint switch array. Each of the N drivers buffers a separate one of the input signals arriving at an input terminal into the crosspoint switch array and each the M receivers buffers an array output signal onto a separate one of the output terminals. The crosspoint switch array provides the necessary routing signal paths.
In accordance with one aspect of the invention, the crosspoint array is formed by rows and/or columns of crosspoint switch sub-arrays, wherein each row of sub-arrays receives input signals from a corresponding subset of the input drivers and each column of sub-arrays forwards signals to a separate subset of receivers.
In accordance with another aspect of the invention, when the crosspoint switch cell array includes more than one column of sub-arrays, each sub-array has an associated set of input buffers for buffering outputs of the input signal drivers into the sub-array rows. Therefore each input signal driver that forwards an input signal to the sub-arrays of a given row need charge or discharge only the input capacitance of the buffers for that row and need not charge any capacitance of the sub-arrays themselves. The sub-array buffers handle that task. Since several buffers provide array capacitance charging or discharging current, they can quickly charge or discharge the signal path capacitance when an input signal changes state. Thus segmenting the crosspoint switch into more than one column of sub-arrays reduces signal path delay through the crosspoint switch because it reduces the time required to charge and discharge the array""s capacitance.
In accordance with a further aspect of the invention, when the crosspoint switch array includes more than one row of sub-arrays, a set of output buffers (implemented, for example, by a set of OR gates) are provided to separately buffer the output signals of the various sub-arrays of each row onto the inputs of the switch""s output drivers. The sub-array output buffers isolate output capacitances of the sub-arrays from one another so that input buffers need only charge or discharge the output capacitance of a particular sub-array that is currently routing a signal to a given output buffer. Thus segmenting the crosspoint switch into more than one row of sub-arrays also reduces signal path delay through the crosspoint switch because it also reduces the time required to charge and discharge signal path capacitance.
It is accordingly an object of the invention to provide a segmented crosspoint switch having relatively low signal path delay.
The concluding portion of this specification the art will best understand both the organization and method of operation of the invention, together with further advantages and objects thereof, by reading the remaining portions of the specification in view of the accompanying drawing(s) wherein like reference characters refer to like elements.